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MX29F022/022NT/B
2M-BIT[256K x 8]CMOS FLASH MEMORY
FEATURES
* 262,144x 8 only * Fast access time: 55/70/90/120ns * Low power consumption
- 30mA maximum active current - 1uA typical standby current@5MHz Programming and erasing voltage 5V10% Command register architecture - Byte Programming (7us typical) - Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte x1, and 64K-Byte x 3) Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors or the whole chip with Erase Suspend capability. - Automatically programs and verifies data at specified address Erase Suspend/Erase Resume - Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation.
* Status Reply
- Data polling & Toggle bit for detection of program and erase cycle completion. Chip protect/unprotect for 5V only system or 5V/12V system 100,000 minimum erase/program cycles Latch-up protected to 100mA from -1 to VCC+1V Boot Code Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector Hardware RESET pin - Resets internal state machine to read mode Low VCC write inhibit is equal to or less than 3.2V Package type: - 32-pin PDIP - 32-pin PLCC - 32-pin TSOP (Type 1) 20 years data retention
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GENERAL DESCRIPTION
The MX29F022T/B is a 2-mega bit Flash memory organized as 256K bytes of 8 bits only. MXIC's Flash memories offer the most cost-effective and reliable read/ write non-volatile random access memory. The MX29F022T/B is packaged in 32-pin PDIP, PLCC and 32-pin TSOP(I). It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers. The standard MX29F022T/B offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F022T/B has separate chip enable (CE) and output enable (OE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F022T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC's Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F022T/ B uses a 5.0V 10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
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PIN CONFIGURATIONS
32 PDIP
NC on MX29F022NT/B
A11 A9 A8 A13 A14 A17 WE VCC RESET A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3
32 TSOP (TYPE 1)
RESET A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3
MX29F022T/B
(NC on MX29F022NT/B)
MX29F022T/B
(NORMAL TYPE)
32 PLCC
NC on MX29F022NT/B
RESET
VCC
A12
A15
A16
A17
WE
SECTOR STRUCTURE
A14 A13 A8 A9
A7 A6 A5 A4 A3 A2 A1 A0 Q0
5
4
1
32
30 29
A17~A0 3FFFFH 3BFFFH
16 K-BYTE (BOOT SECTOR) 8 K-BYTE K-BYTE K-BYTE K-BYTE K-BYTE K-BYTE
9
MX29F022T/B
25
A11 OE A10 CE
39FFFH 8 37FFFH 2FFFFH 64 1FFFFH 64 0FFFFH 64 00000H 32
13 14
17
21 20
Q7
Q1
Q2
VSS
Q3
Q4
Q5
Q6
PIN DESCRIPTION:
A17~A0
MX29F022T Sector Architecture
SYMBOL A0~A17 Q0~Q7 CE WE RESET OE VCC GND
PIN NAME Address Input Data Input/Output Chip Enable Input Write Enable Input Hardware Reset Pin/Sector Protect Unlock Output Enable Input Power Supply Pin (+5V) Ground Pin
3FFFFH 64 2FFFFH 64 1FFFFH 0FFFFH 07FFFH 05FFFH 03FFFH 00000H 8 8 K-BYTE K-BYTE 64 32 K-BYTE K-BYTE K-BYTE K-BYTE
16 K-BYTE (BOOT SECTOR)
MX29F022B Sector Architecture
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BLOCK DIAGRAM
CONTROL CE OE WE RESET INPUT LOGIC
WRITE PROGRAM/ERASE STATE HIGH VOLTAGE MACHINE (WSM)
STATE MX29F022T/B FLASH ARRAY ARRAY SOURCE HV REGISTER
X-DECODER
ADDRESS LATCH A0-A17 AND BUFFER
Y-DECODER
Y-PASS GATE
COMMAND DATA DECODER
SENSE AMPLIFIER
PGM DATA HV
COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q7
I/O BUFFER
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AUTOMATIC PROGRAMMING
The MX29F022T/B is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm does not require the system to time out or verify the data programmed. The typical chip programming time of the MX29F022T/B at room temperature is less than 2 seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, verifies the erase, and counts the number of sequences. A status bit similar to DATA polling and status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation. Commands are written to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle addresses are latched on the falling edge, and data are latched on the rising edge of WE . MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29F022T/B electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10ms erase pulses according to MXIC's High Reliability Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than two second. The device is erased using the Automatic Erase algorithm. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are internally controlled within the device.
AUTOMATIC SECTOR ERASE
The MX29F022T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are internally controlled by the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the user to only write a program set-up commands (include 2 unlock write cycle and A0H) include 2 unlock write cycle and A0H and a program command (program data and address). The device automatically times the programming pulse width, verifies the program verification, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provides feedback to the user as to the status of the programming operation.
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TABLE 1. SOFTWARE COMMAND DEFINITIONS
First Bus Command Reset Read Read Silicon ID Chip Protect Verify Program Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume Unlock for chip protect/unprotect Note: 1. ADI = Address of Device identifier; A1=0,A0 =0 for manufacture code,A1=0, A0 =1 for device code (Refer to Table 3). DDI = Data of Device identifier : C2H for manufacture code, 36H/37H for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA. 2. PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address to the sector to be erased. 3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10. Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A17 in either state. 4. For Chip Protect Verify operation: If read out data is 01H, it means the chip has been protected. If read out data is 00H, it means the chip is still not being protected. Bus Cycle 1 1 4 4 4 6 6 1 1 6 Cycle Addr RA 555H 555H 555H 555H 555H XXXH F0H RD AAH 2AAH 55H AAH 2AAH 55H AAH 2AAH 55H AAH 2AAH 55H AAH 2AAH 55H 555H 90H 555H 90H ADI (SA) DDI 00H PD AAH 2AAH 55H 555H 10H AAH 2AAH 55H SA 30H Second Bus Third Bus Cycle Data Addr Data Cycle Addr Fourth Bus Cycle Data Addr Fifth Bus Cycle Data Addr Sixth Bus Cycle Data Addr Data
X02H 01H 555H A0H PA 555H 80H 555H 80H 555H 555H
XXXH B0H XXXH 30H 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H
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TABLE 2. MX29F022T/B BUS OPERATION
Pins Mode Read Silicon ID Manufacturer Code(1) Read Silicon ID Device Code(1) Read Standby Output Disable Write Chip Protect with 12V system (6) Chip Unprotect with 12V system (6) Verify chip Protect with 12V system Chip Protect without 12V system (6) Chip Unprotect without 12V system (6) Verify Chip Protect/Unprotect without 12V system (7) Reset X X X X X X X HIGH Z L L H X H X H Code(5) L H L X X H H X L H L X X L H X L L H X H X VID(2) Code (5) L VID(2) L X X H VID(2) X L H L L L L X H H VID(2) H X H L L A0 X X A0 X A1 X X A1 X A6 X X A6 L A9 X X A9 VID(2) DOUT HIGH Z HIGH Z DIN(3) X L L H H L X VID(2) 36H/37H L L H L L X VID(2) C2H CE OE WE A0 A1 A6 A9 Q0~Q7
NOTES: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1. 2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V. 3. Refer to Table 1 for valid Data-In during a write operation. 4. X can be VIL or VIH. 5. Code=00H means unprotected. Code=01H means protected. 6. Refer to chip protect/unprotect algorithm and waveform. Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system" command. 7. The "verify chip protect/unprotect without 12V system" is only following "chip protect/unprotect without 12V system" command.
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READ/RESET COMMAND
The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.
SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS
Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H. The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verification begin. The erase and verification operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). If the Erase operation was unsuccessful, the data on Q5 is "1" (see Table 4), indicating the erase operation of exceed internal timing limit. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. The MX29F022T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 36H for MX29F022T, 37H for MX29F022B.
TABLE 3. EXPANDED SILICON ID CODE
Pins Manufacture code Device code for MX29F022T Device code for MX29F022B Chip Protection Verification A0 VIL VIH VIH X X A1 VIL VIL VIL VIH VIH Q7 1 0 0 0 0 Q6 1 0 0 0 0 Q5 0 1 1 0 0 Q4 0 1 1 0 0 Q3 0 0 0 0 0 Q2 0 1 1 0 0 Q1 1 1 1 0 0 Q0 0 0 1 1 0 Code(Hex) C2H 36H 37H 01H (Protected) 00H (Unprotected)
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SET-UP AUTOMATIC SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system does not require to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verification begin. The erase and verification operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system does not required to provide any control or timing during these operations. When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command-80H. Two more "unlock" write cycles are then followed by the sector erase command-30H. The sector address is latched on the falling edge of WE, while the command(data) is latched on the rising edge of WE. Sector addresses selected are loaded into internal register on the sixth falling edge of WE. Each successive sector load cycle started by the falling edge of WE must begin within 30us from the rising edge of the preceding WE. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase (30H) or Erase Suspend (B0H) during the time-out period resets the device to read mode. eration. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and Program commands. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors.
ERASE SUSPEND
This command is only valid while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic/Sector Erase operation. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase op-
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TABLE 4. WRITE OPERATION STATUS
Status Q7 Note1 Byte Program in Auto Program Algorithm Auto Erase Algorithm Erase Suspend Read In Progress Erase Suspended Mode (Erase Suspended Sector) Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program Byte Program in Auto Program Algorithm Exceeded Auto Erase Algorithm Time Limits Erase Suspend Program Q7 Q7 0 Q7 Toggle Toggle Toggle Toggle 0 1 1 1 N/A N/A 1 N/A N/A No Toggle Toggle N/A Data Q7 0 1 Toggle Toggle No Toggle Data Data Data Data Q6 Q5 Note2 0 0 0 N/A 1 N/A No Toggle Toggle Toggle Q3 Q2
Note: 1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5 : Exceeded Timing Limits" for more information.
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ERASE RESUME
This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing. rising edge of the second WE pulse of the two write pulse sequences. While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is compete. Upon completion of the erase operation, the data on Q7 will read "1". The Data Polling feature is valid after the rising edge of the second WE pulse of two write pulse sequences. The Data Polling feature is active during Automatic Program/Erase algorithm or sector erase time-out. (see section Q3 Sector Erase Timer)
SET-UP AUTOMATIC PROGRAM COMMANDS
To initiate Automatic Program mode, A three-cycle command sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Program command A0H. Once the Automatic Program command is initiated, the next WE pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE pulse. The rising edge of WE also begins the programming operation. The system does not require to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin. If the program operation was unsuccessful, the data on Q5 is "1", indicating the program operation of internally exceed timing limit. The automatic programming operation is complete when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode(no program verify command is required).
Q6 : Toggle BIT I
The MX29F022T/B features a "Toggle Bit" as a method to indicate to the host system that the Auto Program/ Erase algorithms are either in progress or complete. During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if the chip is protected, Q6 toggles and returns to reading array data. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7(see the subsection on Q7 : Data Polling). If a program address falls within a protected sector, Q6 toggles for approximately 2us after the program command sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on Q6. Refer to the toggle bit algorithm.
WRITE OPERATION STATUS DATA POLLINGQ7
The MX29F022T/B also features Data Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed. While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data Polling feature is valid after the
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Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit I is valid after the rising edge of the final WE pulse in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 4 to compare outputs for Q2 and Q6. status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of the toggle bit algorithm flow chart).
Q5 Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions not of the device under this condition. If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used.
Reading Toggle Bits Q6/ Q2
Refer to the toggle bit algorithm for the following discussion. Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the
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Q3 Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND.
CHIP PROTECTION WITH 12V SYSTEM
The MX29F022T/B features hardware chip protection, which will disable both program and erase operations. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL.(see Table 2) Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated on the rising edge. Please refer to chip protect algorithm and waveform. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH. When A1=1, it will produce a logical "1" code at device output Q0 for the protected status. Otherwise the device will produce 00H for the unprotected status. In this mode, the addresses, except for A1, are in "don't care" state. Address locations with A1 = VIL are reserved to read manufacturer and device codes.(Read Silicon ID) It is also possible to determine if the chip is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected status.
DATA PROTECTION
The MX29F022T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
CHIP UNPROTECT WITH 12V SYSTEM
The MX29F022T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. To activate this mode, the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE pulse and is terminated on the rising edge. It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns (typical) on CE or WE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
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Performing a read operation with A1=VIH, it will produce 00H at data outputs (Q0-Q7) for an unprotected chip. It is noted that all sectors are unprotected after the chip unprotect algorithm is complete.
ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 VALUE 0oC to 70oC -65oC to 125oC -0.5V to 7.0V -0.5V to 7.0V -0.5V to 7.0V -0.5V to 13.5V
CHIP PROTECTION WITHOUT 12V SYSTEM
The MX29F022T/B also feature a hardware chip protection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to protect all sectors. The details are shown in chip protect algorithm and waveform.
CHIP UNPROTECT WITHOUT 12V SYSTEM
The MX29F022T/B also feature a hardware chip unprotection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to unprotect all sectors. The details are shown in chip unprotect algorithm and waveform.
NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change.
POWER-UP SEQUENCE
The MX29F022T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of a two-step command sequence. Vpp and Vcc power up sequence is not required.
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MX29F022/022NT/B
TEMPORARY SECTOR UNPROTECT OPERATION (only for 29F022T/B)
Start
RESET = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET = VIH Temporary Sector Unprotect Completed(Note 2)
Note : 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V 2. All previously protected sectors are protected again.
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MX29F022/022NT/B
TEMPORARY SECTOR UNPROTECT
Parameter Std. Description tVIDR tRSP Note: Not 100% tested VID Rise and Fall Time (See Note) RESET Setup Time for Temporary Sector Unprotect Test Setup All Speed Options Min Min 500 4 Unit ns us
TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM (only for 29F022T/B)
12V
RESET
0 or 5V Program or Erase Command Sequence 0 or 5V tVIDR
tVIDR
CE
WE
tRSP
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MX29F022/022NT/B
AC CHARACTERISTICS
Parameter Std tREADY tRP1 tRP2 tRH Note: Not 100% tested Description RESET PIN Low (Not During Automatic Algorithms) to Read or Write (See Note) RESET Pulse Width (During Automatic Algorithms) RESET Pulse Width (NOT During Automatic Algorithms) RESET High Time Before Read(See Note) MIN MIN MIN 10 500 0 us ns ns Test Setup All Speed Options Unit MAX 500 ns
RESET TIMING WAVEFORM (only for 29F002T/B)
CE, OE
tRH
RESET
tRP2 tReady
Reset Timing NOT during Automatic Algorithms
RESET
tRP1
Reset Timing during Automatic Algorithms
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MX29F022/022NT/B
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL CIN1 CIN2 COUT PARAMETER MIN. Input Capacitance Control Pin Capacitance Output Capacitance TYP MAX. 8 12 12 UNIT pF pF pF CONDITIONS VIN = 0V VIN = 0V VOUT = 0V
READ OPERATION DC CHARACTERISTICS TA = 0oC TO 70oC, VCC = 5V 10% (VCC=5V 5% for 29F022/022N-55)
SYMBOL ILI ILO ISB1 ISB2 ICC1 ICC2 VIL VIH VOL VOH1 VOH2 PARAMETER Input Leakage Current Output Leakage Current Standby VCC current Operating VCC current Input Low Voltage -0.3(NOTE1) Input High Voltage 2.0 Output Low Voltage Output High Voltage(TTL) 2.4 Output High Voltage(CMOS)VCC-0.4 MIN. TYP MAX. 1 10 1 5 30 50 0.8 VCC + 0.3 0.45 UNIT mA mA mA uA mA mA V V V V V CONDITIONS VIN = GND to VCC VOUT = GND to VCC CE = VIH CE = VCC + 0.3V IOUT = 0mA, f=5MHz IOUT = 0mA, f=10MHz
1
IOL = 2.1mA IOH =-2mA IOH =-100uA,VCC=VCC MIN
NOTES:
1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns. VIL min. = -2.0V for pulse width is equal to or less than 20 ns. 2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns If VIH is over the specified maximum value, read operation cannot be guaranteed.
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MX29F022/022NT/B
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10%(VCC = 5V 5% for 29F022T/B-55)
SYMBOL tACC tCE tOE tDF tOH PARAMETER Address to Output Delay CE to Output Delay OE to Output Delay OE High to Output Float (Note1) Address to Output hold 29F022T/B-55 MIN. MAX. 55 55 25 0 20 0 29F022T/B-70 MIN. MAX. 70 70 30 0 20 0 UNIT ns ns ns ns ns CONDITIONS CE=OE=VIL OE=VIL CE=VIL CE=VIL CE=OE=VIL
SYMBOL PARAMETER tACC tCE tOE tDF tOH Address to Output Delay CE to Output Delay OE to Output Delay OE High to Output Float (Note1) Address to Output hold
29F022T/B-90 MIN. MAX. 90 90 40 30
29F022T/B-120 MIN. MAX. 120 120 50 30
UNIT CONDITIONS ns ns ns ns ns CE=OE=VIL OE=VIL CE=VIL CE=VIL CE=OE=VIL
0 0
0 0
TEST CONDITIONS:
* Input pulse levels: 0.45V/2.4V for 70ns max.
: 0V/3V for 55ns speed grade. * Input rise and fall times: < 10ns for 70ns max. : < 5ns for 55ns speed grade. * Output load: 1 TTL gate + 100pF(Including scope and jig) for 70ns max. : 1 TTL gate + 50pF(Including scope and jig) for 55ns speed grade. * Reference levels for measuring timing : 0.8V/2.0V or 70ns max. :1.5V/1.5V for 55ns speed grade.
NOTE: 1.tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
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MX29F022/022NT/B
READ TIMING WAVEFORMS
VIH
A0~17
VIL
ADD Valid
tCE VIH
CE
VIL
WE
VIH VIL VIH VIL tACC tOH tOE tDF
OE
DATA Q0~7
VOH VOL
HIGH Z
DATA Valid
HIGH Z
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MX29F022/022NT/B
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10%(VCC = 5V 5% for 29F022/022N-55)
SYMBOL ICC1 (Read) ICC2 ICC3 (Program) ICC4 (Erase) ICCES VCC Erase Suspend Current 2 PARAMETER Operating VCC Current MIN. TYP MAX. UNIT CONDITIONS 30 50 50 50 mA mA mA mA mA IOUT=0mA, f=5MHz IOUT=0mA, F=10MHz In Programming In Erase CE=VIH, Erase Suspended
NOTES: 1. VIL min. = -0.6V for pulse width is equal to or less than 20ns. 2. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2. 4. All current are in RMS unless otherwise noted.
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MX29F022/022NT/B
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10%(VCC=5V5% for 29F022T/B-55)
29F022T/B-55(Note2) 29F022T/B-70 29F022T/B-90 SYMBOL tOES tCWC tCEP tCEPH1 tCEPH2 tAS tAH tDS tDH tCESC tDF tAETC tAETB tAVT tBAL tCH tCS tVLHT tOESP tWPP1 tWPP2 PARAMETER OE setup time Command programming cycle WE programming pulse width WE programming pulse width High WE programming pulse width High Address setup time Address hold time Data setup time Data hold time CE setup time before command write Output disable time (Note 1) Total erase time in auto chip erase Total erase time in auto sector erase Total programming time in auto verify (Byte Program time) Sector address load time CE Hold Time CE setup to WE going low Voltage Transition Time OE Setup Time to WE Active Write pulse width for chip protect Write pulse width for chip unprotect 100 0 0 4 4 10 12 100 0 0 4 4 10 12 100 0 0 4 4 10 12 100 0 0 4 4 10 12 us us us us us us ms MIN. 0 70 45 20 20 0 45 20 0 0 20 3(TYP.) 24 1(TYP.) 8 7(TYP.) 210 MAX. MIN. 0 70 45 20 20 0 45 30 0 0 30 3(TYP.) 24 1(TYP.) 8 7(TYP.) 210 MAX. MIN. 0 90 45 20 20 0 45 45 0 0 40 3(TYP.) 24 1(TYP.) 8 7(TYP.) 210 29F022T/B-12 MAX. UNIT ns ns ns ns ns ns ns ns ns ns 40 3(TYP.) 24 1(TYP.) 8 7(TYP.) 210 ns s s us
MAX. MIN. 0 120 50 20 20 0 50 50 0 0
NOTES: 1.tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2.Under condition of VCC=5V5%,CL=50pF, VIH/VIL=3.0V/0V, VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA.
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MX29F022/022NT/B
SWITCHING TEST CIRCUITS
DEVICE UNDER TEST
1.6K ohm
+5V
CL
1.2K ohm
DIODES=IN3064 OR EQUIVALENT
CL=100pF Including jig capacitance for 29F022/022N-70, 29F022/022N-90,29F022/022N-12 CL=50pF Including jig capacitance for 29F022/022N-55
SWITCHING TEST WAVEFORMS(I) for MX29F022/022N-70/90/120
2.4V
2.0V
2.0V
TEST POINTS
0.8V
0.45V INPUT
0.8V OUTPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are <20ns.
SWITCHING TEST WAVEFORMS(I) for MX29F022/022N-55
3.0V
1.5V
TEST POINTS
1.5V
0V INPUT
OUTPUT
AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns.
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MX29F022/022NT/B
COMMAND WRITE TIMING WAVEFORM
VCC
5V
ADD A0~17
VIH
ADD Valid
VIL tAS tAH
WE
VIH VIL tOES tCEPH1 tCWC
tCEP
CE
VIH VIL tCS tCH
OE
VIH VIL VIH tDS tDH
DATA Q0-7
DIN
VIL
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MX29F022/022NT/B
AUTOMATIC PROGRAMMING TIMING WAVEFORM
One byte data is programmed. Verifying in fast algorithm and additional programming by external control are not required because these operations are executed automatically by internal control circuit. Programming completion can be verified by DATA polling and toggle bit checking after automatic verification star ts. Device outputs DATA during programming and DATA after programming on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)
AUTOMATIC PROGRAMMING TIMING WAVEFORM
Vcc 5V
A11~A17
ADD Valid
A0~A10 WE
555H
2AAH
555H
ADD Valid
tAS tAH
tCWC tCEPH1 tAVT tCESC
CE tCEP OE tDS Q0~Q1 ,Q4(Note 1) Q7
Command In Command #AAH Command In Command #55H Command In Command #A0H Data In
tDH
Command In Command In Data In DATA
tDF
Command In
DATA polling
DATA DATA
(Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2:Toggle bit
tOE
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MX29F022/022NT/B
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Toggle Bit Checking Q6 not Toggled YES
NO
Invalid Command
NO Verify Byte Ok YES NO Auto Program Completed Q5 = 1 YES
.
Reset
Auto Program Exceed Timing Limit
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MX29F022/022NT/B
TOGGLE BIT ALGORITHM
START
Read Q7~Q0
Read Q7~Q0
(Note 1)
Toggle Bit Q6 =Toggle? YES
NO
NO Q5=1?
YES Read Q7~Q0 Twice (Note 1,2)
Toggle Bit Q6 =Toggle? YES Program/Erase Operation Not Complete, Write Reset Command
Program/Erase Operation Complete
Notes: 1.Read toggle bit Q6 twice to determine whether or not it is toggle. See text. 2.Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See text.
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MX29F022/022NT/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase starts. Device outputs "0" during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM
Vcc 5V
A11~A17
A0~A10 WE
555H
2AAH
555H
555H
2AAH
555H
tAS tAH
tCWC tCEPH1
tAETC
CE tCEP OE tDS tDH Q0,Q1, Q4(Note 1) Q7
Command In Command #AAH Command In Command #55H Command In Command #80H Command In Command #AAH Command In Command #55H Command In Command #10H Command In Command In Command In Command In Command In Command In
DATA polling
(Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
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MX29F022/022NT/B
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Toggle Bit Checking Q6 not Toggled YES
NO
Invalid Command
NO
DATA Polling Q7 = 1
YES NO Auto Chip Erase Completed Q5 = 1
YES Reset
. Auto Chip Erase Exceed Timing-Limit
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MX29F022/022NT/B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector data indicated by A13 to A17 are erased. External erase verification is not required because data are erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform)
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Vcc 5V
A13~A17
Sector Address0
Sector Address1
Sector Addressn
A0~A10
555H tAS tAH
2AAH
555H
555H
2AAH tCWC
WE
tCEPH1 tBAL tAETB
CE
tCEP
OE
tDS tDH
Q0,Q1, Q4(Note 1)
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Command In
DATA polling
Q7
Command In
Command In
Command In
Command In
Command In
Command In
Command In Command #30H
Command In Command #30H
Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H (Q0~Q7)
Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
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MX29F022/022NT/B
AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Toggle Bit Checking Q6 Toggled ?
NO Invalid Command
YES Load Other Sector Addrss If Necessary (Load Other Sector Address)
Last Sector to Erase YES
NO
Time-out Bit Checking Q3=1 ?
NO
YES NO
Toggle Bit Checking Q6 not Toggled YES
NO DATA Polling Q7 = 1 Q5 = 1
YES Reset Auto Sector Erase Completed
Auto Sector Erase Exceed Timing Limit
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MX29F022/022NT/B
ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
NO Toggle Bit checking Q6 not toggled YES Read Array or Program
Reading or Programming End YES Write Data 30H
NO
Continue Erase
Another Erase Suspend ? YES
NO
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MX29F022/022NT/B
TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITH 12V
A1
A6
12V 5V A9
tVLHT Verify
12V 5V OE
tVLHT tWPP 1 tVLHT
WE
tOESP
CE
Data
tOE
01H
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V
A1
12V 5V A9
tVLHT
A6
Verify
12V 5V OE
tVLHT tWPP 2 tVLHT
WE
tOESP
CE
Data
tOE
00H
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MX29F022/022NT/B
CHIP PROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
PLSCNT=1
OE=VID,A9=VID,CE=VIL A6=VIL
Activate WE Pulse
Time Out 10us Device Failed Set WE=VIH, CE=OE=VIL A9 should remain VID
No
Read from Sector Addr=SA, A1=1
PLSCNT=32?
No
Data=01H?
Yes Device Failed
Yes Remove VID from A9 Write Reset Command
Chip Protection Complete
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MX29F022/022NT/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
PLSCNT=1
Set OE=A9=VID CE=VIL,A6=1
Activate WE Pulse
Time Out 12ms
Increment PLSCNT
Set OE=CE=VIL A9=VID,A1=1
Read Data from Device No
Data=00H?
No PLSCNT=1000?
Yes Remove VID from A9 Write Reset Command
Yes Device Failed
Chip Unprotect Complete
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MX29F022/022NT/B
TIMING WAVEFORM FOR CHIP PROTECTION/UNPROTECTION FOR SYSTEM WITHOUT 12V
A6,A9 & sector address are don't care during toggle bit polling period, or just be kept valid value in read window.
6th command cycle : 555H
7th command cycle
Protected Verify '1'
Reset to Read Mode X
A1
X
'0' '1'
X=Don't care
tACC
A6
X
X
(Note 2) '0'
X
A9
X
'0'
X
X
X
OE
tAS tAH tOE
WE
A6,A9 and Sector Addr. should be latched on the falling e dge of WE or CE , ehich occurs last, for WSM reference
CE
tCEP
Toggle Bit Polling X(2)
Dout Dout Dout
tCE Dout F0H
(Q0-Q7)
20H
Note1: Don't care except F0H. Note2: Protection:7th command cycle A6 goes low. Unprotection: 7th command cycle A6 goes high. Note3: Protection verify:01H Un-protection verify:00H Note4: Must issue "unlock for chip protection/unprotection" command before chip protection/un-protection for a system without 12V provided.
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MX29F022/022NT/B
CHIP PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "Unlock for chip protect/unprotect" Command
OE=VID,A9=VID CE=VIL,A6=VIL
Activate WE Pulse to start Data don't care
Toggle bit checking Q6 not Toggle Yes Increment PLSCNT Set CE=OE=VIL A9=VIH
No
.
Read from Sector Addr. =SA,A1=1 No No
PLSCENT=32?
Data=01H?
Yes Device Failed
Yes Write Reset Command
Chip Protection Complete
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MX29F022/022NT/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for chip protect/unprotect" Command (Table 1)
Set OE=A9=VIH CE=VIL,A6=1
Activate WE Pulse to start Data don't care
No
Toggle bit checking Q6 not Toggled Yes Set OE=CE=VIL A9=VIH,A1=1
Increment PLSCNT
Read Data from Device No
Data=00H?
No
PLSCNT=1000?
Yes Write Reset Command
Yes Device Failed
Chip Unprotect Complete
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MX29F022/022NT/B
ID CODE READ TIMING WAVEFORM MODE
VCC
5V VID VIH VIL
ADD A9
tACC
tACC
A1
VIH VIL
ADD A2-A8 A10-A17 CE
VIH VIL
VIH VIL
WE
VIH VIL
tCE
OE
VIH VIL
tOE tDF tOH tOH
VIH
DATA Q0-Q7
DATA OUT
VIL
DATA OUT 36H/37H
C2H
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MX29F022/022NT/B
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO. MX29F022TPC-55 MX29F022TPC-70 MX29F022TPC-90 MX29F022TPC-12 MX29F022TTC-55 MX29F022TTC-70 MX29F022TTC-90 MX29F022TTC-12 MX29F022TQC-55 MX29F022TQC-70 MX29F022TQC-90 MX29F022TQC-12 MX29F022BPC-55 MX29F022BPC-70 MX29F022BPC-90 MX29F022BPC-12 MX29F022BTC-55 MX29F022BTC-70 MX29F022BTC-90 MX29F022BTC-12 MX29F022BQC-70 MX29F022BQC-90 MX29F022BQC-12 MX29F022NTPC-55 MX29F022NTPC-70 MX29F022NTPC-90 MX29F022NTPC-12 ACCESS TIME (ns) 55 70 90 120 55 70 90 120 55 70 90 120 55 70 90 120 55 70 90 120 70 90 120 55 70 90 120 OPERATING CURRENT MAX.(mA) 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 STANDBY CURRENT MAX.(uA) 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 32 Pin PDIP 32 Pin PDIP 32 Pin PDIP 32 Pin PDIP 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC 32 Pin PDIP 32 Pin PDIP 32 Pin PDIP 32 Pin PDIP 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC 32 Pin PDIP 32 Pin PDIP 32 Pin PDIP 32 Pin PDIP PACKAGE
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MX29F022/022NT/B
PART NO. MX29F022NTTC-55 MX29F022NTTC-70 MX29F022NTTC-90 MX29F022NTTC-12 MX29F022NTQC-55 MX29F022NTQC-70 MX29F022NTQC-90 MX29F022NTQC-12 MX29F022NBPC-55 MX29F022NBPC-70 MX29F022NBPC-90 MX29F022NBPC-12 MX29F022NBTC-55 MX29F022NBTC-70 MX29F022NBTC-90 MX29F022NBTC-12 MX29F022NBQC-70 MX29F022NBQC-90 MX29F022NBQC-12 ACCESS TIME (ns) 55 70 90 120 55 70 90 120 55 70 90 120 55 70 90 120 70 90 120 OPERATING CURRENT MAX.(mA) 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 STANDBY CURRENT MAX.(uA) 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC 32 Pin PDIP 32 Pin PDIP 32 Pin PDIP 32 Pin PDIP 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin TSOP (Normal Type) 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC PACKAGE
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MX29F022/022NT/B
ERASE AND PROGRAMMING PERFORMANCE (1)
PARAMETER
Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles 100,000
MIN.
LIMITS TYP.(2)
1 3 7 3.5
MAX.(3)
8 24 210 10.5
UNITS
s s us sec Cycles
Note:
1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25 C,5V. 3.Maximum value measured at 25 C,4.5V.
LATCH-UP CHARACTERISTICS
MIN. Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. -1.0V -1.0V -100mA MAX. 13.5V Vcc + 1.0V +100mA
DATA RETENTION
PARAMETER Data Retention Time MIN. 20 UNIT Years
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PACKAGE INFORMATION
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MX29F022/022NT/B
REVISION HISTORY
Revision 1.0 Description 1.To remove "Advanced Information" data sheet marking and contain information on products in full production 2.The modification summary of Revision 0.9.4 to Revision 1.0: 2-1.Program/erase cycle times:10K cycles-->100K cycles 2-2.To add data retention 20 years 2-3.To remove A9 from the timing waveform of protection/ unprotection without 12V 2-4.Multi-sector erase time-out:30ms-->30us, 2-5.tBAL:80us-->100us To modify "Package Information" 1. To correct typing error 1. To change part no. from MX29F022/022N to MX29F022/022NT/B Page P1 Date DEC/21/1999
P1,41 P1,41 P35 P8 P21 P42~44 All All
1.1 1.2 1.3
JUN/14/2001 JUN/11/2002 NOV/11/2002
P/N:PM0556
REV. 1.3, NOV. 11, 2002
45
MX29F022/022NT/B
MACRONIX INTERNATIONAL CO., LTD.
Headquarters:
TEL:+886-3-578-6688 FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020 FAX:+32-2-456-8021
Hong Kong Office :
TEL:+86-755-834-335-79 FAX:+86-755-834-380-78
Japan Office :
Kawasaki Office :
TEL:+81-44-246-9100 FAX:+81-44-246-9105
Osaka Office :
TEL:+81-6-4807-5460 FAX:+81-6-4807-5461
Singapore Office :
TEL:+65-6346-5505 FAX:+65-6348-8096
Taipei Office :
TEL:+886-2-2509-3300 FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-262-8887 FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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